View ST16C454_5771381.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

exar corporation, 48720 kato road, fremont, ca 94538 (510) 668-7000 fax (510) 668-7017 ST16C454 st68c454 rev. 3.20 quad universal asynchronous receiver/transmitter (uart) description the ST16C454 is a universal asynchronous receiver and transmitter (uart) with a dual foot print interface. the 454 is an enhanced uart with data rates up to 1.5mbps and software compatible to st16c450. onboard status registers provide the user with error indications and operational status, modem interface control. system interrupts may be tailored to meet user requirements. an internal loop-back capability allows onboard diagnostics. the ST16C454 offer an additional 68 mode which allows easy integration with motorola, and other popular microprocessors. the 454 combines the package interface modes of the ST16C454 and st68c454 series on a single inte- grated chip. features software compatibility with the industry standard 16c450 1.5 mbps transmit/receive operation (24mhz) independent transmit and receive control software selectable baud rate generator modem control signals (-cts, -rts, -dsr, -dtr, -ri, -cd) programmable character lengths (5, 6, 7, 8) even, odd, or no parity bit generation and detection internal loop-back diagnostics ttl compatible inputs, outputs low power ordering information part number pins package o perating temperature ST16C454cj68 68 plcc 0 c to + 70 c ST16C454ij68 68 plcc -40 c to + 85 c 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 -dsra -ctsa -dtra vcc -rtsa inta -csa txa -iow txb -csb intb -rtsb gnd -dtrb -ctsb -dsrb -cdb -rib rxb vcc 16/-68 a2 a1 a0 xtal1 xtal2 reset n.c. n.c. gnd rxc -ric -cdc -dsrd -ctsd -dtrd gnd -rtsd intd -csd txd -ior txc -csc intc -rtsc vcc -dtrc -ctsc -dsrc -cda -ria rxa gnd d7 d6 d5 d4 d3 d2 d1 d0 intsel vcc rxd -rid -cdd ST16C454cj68 16 mode plcc package 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 -dsra -ctsa -dtra vcc -rtsa -irq -cs txa r/-w txb a3 n.c. -rtsb gnd -dtrb -ctsb -dsrb -cdb -rib rxb vcc 16/-68 a2 a1 a0 xtal1 xtal2 -reset n.c. n.c. gnd rxc -ric -cdc -dsrd -ctsd -dtrd gnd -rtsd n.c. n.c. txd n.c. txc a4 n.c. -rtsc vcc -dtrc -ctsc -dsrc -cd a -ria rxa gnd d7 d6 d5 d4 d3 d2 d1 d0 n.c. vcc rxd -rid -cd d ST16C454cj68 68 mode
ST16C454/68c454 2 rev. 3.20 figure 2, block diagram 16 mode d0-d7 -ior -iow reset a0-a2 -cs a-d i nt a-d intsel -dtr a-d -rts a-d -cts a-d -ri a-d -cd a-d -dsr a-d tx a-d rx a-d xtal1 xtal2 data bus & control logic register select logic modem control logic interrupt control logic transmit holding registers transmit shift register receive holding registers receive shift register inter connect bus lines & control signals clock & baud rate generator
ST16C454/68c454 3 rev. 3.20 d0-d7 r/-w -reset a0-a4 -cs -irq -dtr a-d -rts a-d -cts a-d -ri a-d -cd a-d -dsr a-d tx a-d rx a-d xtal1 xtal2 data bus & control logic register select logic modem control logic interrupt control logic transmit holding registers transmit shift register receive holding registers receive shift register inter connect bus lines & control signals clock & baud rate generator figure 3, block diagram 68 mode
ST16C454/68c454 4 rev. 3.20 16/-68 31 i 16/68 interface type select (input with internal pull-up). - this input provides the 16 (intel) or 68 (motorola) bus interface type select. the functions of -ior, -iow, int a-d, and -cs a-d are re- assigned with the logical state of this pin. when this pin is a logic 1, the 16 mode interface ST16C454 is selected. when this pin is a logic 0, the 68 mode interface (st68c454) is selected. when this pin is a logic 0, -iow is re-assigned to r/-w, reset is re-assigned to -reset, -ior is not used, and int a-d(s) are connected in a wire-or? configuration. the wire-or outputs are connected internally to the open source irq signal output. a0 34 i address-0 select bit. internal registers address selection in 16 and 68 modes. a1 33 i address-1 select bit. internal registers address selection in 16 and 68 modes. a2 32 i address-2 select bit. - internal registers address selection in 16 and 68 modes. a3-a4 20,50 i address 3-4 select bits. - when the 68 mode is selected, these pins are used to address or select individual uart?s (providing - cs is a logic 0). in the 16 mode, these pins are reassigned as chip selects, see -csb and -csc. -cs 16 i chip select. (active low) - in the 68 mode, this pin functions as a multiple channel chip enable. in this case, all four uart?s (a-d) are enabled when the -cs pin is a logic 0. an individual uart channel is selected by the data contents of address bits a3-a4. when the 16 mode is selected, this pin functions as -csa, see definition under -cs a-b. -cs a-b 16,20 -cs c-d 50,54 i chip select a, b, c, d (active low) - this function is associated with the 16 mode only, and for individual channels, ?a? through ?d.? when in 16 mode, these pins enable data transfers between the user cpu and the ST16C454 for the channel(s) addressed. individual uart sections (a, b, c, d) are addressed by providing a logic 0 on the respective -cs a-d pin. when the 68 mode is selected, the functions of these pins are reassigned. 68 mode functions are described under the their respective name/pin headings. symbol pin signal pin description type symbol description
ST16C454/68c454 5 rev. 3.20 d0-d2 66-68 i/o d3-d7 1-5 data bus (bi-directional) - these pins are the eight bit, three state data bus for transferring information to or from the controlling cpu. d0 is the least significant bit and the first data bit in a transmit or receive serial data stream. gnd 6,23 gnd 40,57 pwr signal and power ground. int a-b 15,21 int c-d 49,55 o interrupt a, b, c, d (active high) - this function is associated with the 16 mode only. these pins provide individual channel inter- rupts, int a-d. int a-d are enabled when mcr bit-3 is set to a logic 1, interrupts are enabled in the interrupt enable register (ier), and when an interrupt condition exists. interrupt conditions in- clude: receiver errors, available receiver buffer data, transmit buffer empty, or when a modem status flag is detected. when the 68 mode is selected, the functions of these pins are reassigned. 68 mode functions are described under the their respective name/pin headings. intsel 65 i interrupt select. (active high, with internal pull-down) - this function is associated with the 16 mode only. when the 16 mode is selected, this pin can be used in conjunction with mcr bit-3 to enable or disable the three state interrupts, int a-d or override mcr bit-3 and force continuous interrupts. interrupt outputs are enabled continuously by making this pin a logic 1. making this pin a logic 0 allows mcr bit-3 to control the three state interrupt output. in this mode, mcr bit-3 is set to a logic ?1? to enable the three state outputs. this pin is disabled in the 68 mode. -ior 52 i read strobe. (active low strobe) - this function is associated with the 16 mode only. a logic 0 transition on this pin will load the contents of an internal register defined by address bits a0-a2 onto the ST16C454 data bus (d0-d7) for access by an external cpu. this pin is disabled in the 68 mode. -iow 18 i w rite strobe. (active low strobe) - this function is associated with the 16 mode only. a logic 0 transition on this pin will transfer the contents of the data bus (d0-d7) from the external cpu to an internal register that is defined by address bits a0-a2. when the 16 mode is selected, this pin functions as r/-w, see definition symbol pin signal pin description type symbol description
ST16C454/68c454 6 rev. 3.20 under r/-w. -irq 15 o interrupt request or interrupt ?a? - this function is associated with the 68 mode only. in the 68 mode, interrupts from uart channels a-d are wire-or?ed? internally to function as a single irq interrupt. this pin transitions to a logic 0 (if enabled by the interrupt enable register) whenever a uart channel(s) requires service. individual channel interrupt status can be determined by address- ing each channel through its associated internal register, using - cs and a3-a4. in the 68 mode an external pull-up resistor must be connected between this pin and vcc. the function of this pin changes to inta when operating in the 16 mode, see definition under inta. -reset reset 37 i reset. - in the 16 mode a logic 1 on this pin will reset the internal registers and all the outputs. the uart transmitter output and the receiver input will be disabled during reset time. (see ST16C454 external reset conditions for initialization details.) when 16/-68 is a logic 0 (68 mode), this pin functions similarly but, as an inverted reset interface signal, -reset. r/-w 18 i read/write strobe (active low) - this function is associated with the 68 mode only. this pin provides the combined functions for read or write strobes. a logic 1 to 0 transition transfers the contents of the cpu data bus (d0-d7) to the register selected by -cs and a0-a4. similarly a logic 0 to 1 transition places the contents of a 454 register selected by -cs and a0-a4 on the data bus, d0-d7, for transfer to an external cpu. vcc 13 vcc 47,64 i power supply inputs. xtal1 35 i crystal or external clock input - functions as a crystal input or as an external clock input. a crystal can be connected between this pin and xtal2 to form an internal oscillator circuit (see figure 8). alternatively, an external clock can be connected to this pin to provide custom data rates (see baud rate generator program- ming). xtal2 36 o output of the crystal oscillator or buffered clock - (see also xtal1). crystal oscillator output or buffered clock output. symbol pin signal pin description type symbol description
ST16C454/68c454 7 rev. 3.20 -cd a-b 9,27 -cd c-d 43,61 i carrier detect (active low) - these inputs are associated with individual uart channels a through d. a logic 0 on this pin indicates that a carrier has been detected by the modem for that channel. -cts a-b 11,25 -cts c-d 45,59 i clear to send (active low) - these inputs are associated with individual uart channels, a through d. a logic 0 on the -cts pin indicates the modem or data set is ready to accept transmit data from the 454. status can be tested by reading msr bit-4. -dsr a-b 10,26 -dsr c-d 44,60 i data set ready (active low) - these inputs are associated with individual uart channels, a through d. a logic 0 on this pin indicates the modem or data set is powered-on and is ready for data exchange with the uart. this pin has no effect on the uart?s transmit or receive operation. this pin has no effect on the uart?s transmit or receive operation. -dtr a-b 12,24 -dtr c-d 46,58 o data terminal ready (active low) - these inputs are associated with individual uart channels, a through d. a logic 0 on this pin indicates that the 454 is powered-on and ready. this pin can be controlled via the modem control register. writing a logic 1 to mcr bit-0 will set the -dtr output to logic 0, enabling the modem. this pin will be a logic 1 after writing a logic 0 to mcr bit-0. this pin has no effect on the uart?s transmit or receive operation. -ri a-b 8,28 -ri c-d 42,62 i ring indicator (active low) - these inputs are associated with individual uart channels, a through d. a logic 0 on this pin indicates the modem has received a ringing signal from the telephone line. a logic 1 transition on this input pin will generate an interrupt. -rts a-b 14,22 -rts c-d 48,56 o request to send (active low) - these outputs are associated with individual uart channels, a through d. a logic 0 on the -rts pin indicates the transmitter has data ready and waiting to send. writing a logic 1 in the modem control register (mcr bit-1) will set this pin to a logic 0 indicating data is available. after a reset this pin symbol pin signal pin description type symbol description
ST16C454/68c454 8 rev. 3.20 will be set to a logic 1. this pin has no effect on the uart?s transmit or receive operation. rx a-b 7,29 rx c-d 41,63 i receive data input rx a-d. - these inputs are associated with individual serial channel data to the ST16C454. the rx signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. during the local loop-back mode, the rx input pin is disabled and tx data is internally connected to the uart rx input, internally. tx a-b 17,19 tx c-d 51,53 o transmit data - these outputs are associated with individual serial transmit channel data from the 454. the tx signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. during the local loop-back mode, the tx input pin is disabled and tx data is internally connected to the uart rx input. symbol pin signal pin description type symbol description
ST16C454/68c454 9 rev. 3.20 general description the 454 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-paral- lel data conversions for both the transmitter and receiver sections. these functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. synchronization for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data character (character orientated protocol). data integ- rity is insured by attaching a parity bit to the data character. the parity bit is checked by the receiver for any transmission bit errors. the electronic circuitry to provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip. the ST16C454 represents such an integration with greatly enhanced features. the 454 is fabricated with an advanced cmos process to achieve low drain power and high speed requirements. the 454 combines the package interface modes of the ST16C454 and st68c454 series on a single inte- grated chip. the 16 mode interface is designed to operate with the intel type of microprocessor bus while the 68 mode is intended to operate with motorola, and other popular microprocessors. the 454 is capable of operation to 1.5mbps with a 24 mhz crystal or external clock input. with a crystal of 14.7464 mhz, the user can select data rates up to 921.6kbps. the rich feature set of the 454 is available through internal registers. selectable tx and rx baud rates, modem interface controls. in the 16 mode intsel and mcr bit-3 can be configured to provide a software controlled or continuous interrupt capability. functional descriptions interface options two user interface modes are selectable for the 454 package. these interface modes are designated as the ?16 mode? and the ?68 mode.? this nomenclature corresponds to the early ST16C454 and st68c454 package interfaces respectively. the 16 mode interface the 16 mode configures the package interface pins for connection as a standard 16 series (intel) device and operates similar to the standard cpu interface avail- able on the ST16C454. in the 16 mode (pin 16/-68 logic 1) each uart is selected with individual chip select (-csx) pins as shown in table 2 below. table 2, serial port channel selection guide, 16 mode interface -csa -csb -csc -csd uart channel 1111 none 0111 a 1011 b 1101 c 1110 d the 68 mode interface the 68 mode configures the package interface pins for connection with motorola, and other popular micro- processor bus types. the interface operates similar to the st68c454. in this mode the 454 decodes two additional addresses, a3-a4 to select one of the four uart ports. the a3-a4 address decode function is used only when in the 68 mode (16/-68 logic 0), and is shown in table 3 below. table 3, serial port channel selection guide, 68 mode interface -cs a4 a3 uart channel 1 n/a n/a none 000 a 001 b 010 c 011 d
ST16C454/68c454 10 rev. 3.20 internal registers the 454 provides 12 internal registers for monitoring and control. these resisters are shown in table 4 below. these registers are similar to those already available in the standard 16c450. these registers function as data holding registers (thr/rhr), inter- table 4, internal register decode a2 a1 a0 read mode write mode general register set (thr/rhr, ier/isr, mcr/msr, lcr/lsr, spr): 0 0 0 receive holding register transmit holding register 0 0 1 interrupt enable register 0 1 0 interrupt status register 0 1 1 line control register 1 0 0 modem control register 1 0 1 line status register 1 1 0 modem status register 1 1 1 scratchpad register scratchpad register baud rate register set (dll/dlm): note *2 0 0 0 lsb of divisor latch lsb of divisor latch 0 0 1 msb of divisor latch msb of divisor latch note *2: these registers are accessible only when lcr bit-7 is set to a logic 1. rupt status and control registers (ier/isr), line status and control registers (lcr/lsr), modem status and control registers (mcr/msr), programmable data rate (clock) control registers (dll/dlm), and a user assessable scratchpad register (spr). register func- tions are more fully described in the following para- graphs.
ST16C454/68c454 11 rev. 3.20 programmable baud rate generator the 454 supports high speed modem technologies that have increased input data rates by employing data compression schemes. for example a 33.6kbps modem that employs data compression may require a 115.2kbps input data rate. a 128.0kbps isdn modem that supports data compression may need an input data rate of 460.8kbps. the 454 can support a stan- dard data rate of 921.6kbps. single baud rate generator is provided for the trans- mitter and receiver, allowing independent tx/rx channel control. the programmable baud rate gen- erator is capable of accepting an input clock up to 24 mhz, as required for supporting a 1.5mbps data rate. the 454 can be configured for internal or external clock operation. for internal clock oscillator opera- tion, an industry standard microprocessor crystal (par- allel resonant/ 22-33 pf load) is connected externally between the xtal1 and xtal2 pins (see figure 8). alternatively, an external clock can be connected to the xtal1 pin to clock the internal baud rate generator for standard or custom rates. (see baud rate genera- tor programming). the generator divides the input 16x clock by any divisor from 1 to 2 16 -1. the 454 divides the basic crystal or external clock by 16. further division of this 16x clock provides two table rates to support low and high data rate applications using the same system design. customized baud rates can be achieved by selecting the proper divisor values for the msb and lsb sections of baud rate generator. programming the baud rate generator registers dlm (msb) and dll (lsb) provides a user capability for selecting the desired final baud rate. the example in table 5 below, shows the two selectable baud rate tables available when using a 1.8432mhz or 7.3728 mhz crystal. output output user user dlm dll baud rate baud rate 16 x clock 16 x clock program program (1.8432 mhz (7.3728 mhz divisor divisor value value clock) clock) (decimal) (hex) (hex) (hex) 50 200 2304 900 09 00 300 1200 384 180 01 80 600 2400 192 c0 00 c0 1200 4800 96 60 00 60 2400 9600 48 30 00 30 4800 19.2k 24 18 00 18 9600 38.4k 12 0c 00 0c 19.2k 76.8k 6 06 00 06 38.4k 153.6k 3 03 00 03 57.6k 230.4k 2 02 00 02 115.2k 460.8k 1 01 00 01
ST16C454/68c454 12 rev. 3.20 loop-back mode the internal loop-back capability allows onboard diag- nostics. in the loop-back mode the normal modem interface pins are disconnected and reconfigured for loop-back internally. mcr register bits 0-3 are used for controlling loop-back diagnostic testing. in the loop-back mode op1 and op2 in the mcr register (bits 3/2) control the modem -ri and -cd inputs respectively. mcr signals -dtr and -rts (bits 0-1) are used to control the modem -cts and -dsr inputs respectively. the transmitter output (tx) and the receiver input (rx) are disconnected from their asso- ciated interface pins, and instead are connected to- gether internally (see figure 12). the -cts, -dsr, - cd, and -ri are disconnected from their normal modem control inputs pins, and instead are connected internally to -dtr, -rts, -op1 and -op2. loop-back test data is entered into the transmit holding register via the user data bus interface, d0-d7. the transmit uart serializes the data and passes the serial data to the receive uart via the internal loop-back connec- tion. the receive uart converts the serial data back into parallel data that is then made available at the user data interface, d0-d7. the user optionally com- pares the received data to the initial transmitted data for verifying error free operation of the uart tx/rx circuits. in this mode, the receiver and transmitter interrupts are fully operational. the modem control interrupts are also operational. however, the interrupts can only be read using lower four bits of the modem control register (mcr bits 0-3) instead of the four modem status register bits 4-7. the interrupts are still con- trolled by the ier. c1 22pf c2 33pf x1 1.8432 mhz xta l 1 xta l 2 figure 8, crystal oscillator connection
ST16C454/68c454 13 rev. 3.20 figure 12, internal loop-back mode diagram d0-d7 -ior,-iow reset a0-a2 -cs a-d int a-d tx a-d rx a-d data bus & control logic register select logic modem control logic interrupt control logic transmit holding registers transmit shift register receive holding registers receive shift register inter connect bus lines & control signals clock & baud rate generator xtal1 xtal2 -cts a-d -rts a-d -dtr a-d -dsr a-d -ri a-d -cd a-d (-op1 a-d) (-op2 a-d) mcr bit-4=1
ST16C454/68c454 14 rev. 3.20 register functional descriptions the following table delineates the assigned bit functions for the fifteen 454 internal registers. the assigned bit functions are more fully defined in the following paragraphs. table 6, ST16C454 internal registers a2 a1 a0 register bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 [default] note *5 general register set 0 0 0 rhr[xx] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 0 thr[xx] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 ier[00] 0000m odem receive transmit receive status line holding holding interrupt status register register interrupt 0 1 0 isr[01] 0000intintintint priority priority priority status bit-2 bit-1 bit-0 0 1 1 lcr[00] divisor set set even parity stop word word latch break parity parity enable bits l ength length enable b it-1 bit-0 1 0 0 mcr[00] 0 0 0 loop -op2/ -op1 -rts -dtr back intx enable 1 0 1 lsr[60] 0 trans. trans. break framing parity overrun receive empty holding interrupt error error error data empty ready 1 1 0 msr[x0] cd ri dsr cts delta delta delta delta -cd -ri -dsr -cts 1 1 1 spr[ff] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 special register set: note *2 0 0 0 dll[xx] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 dlm[xx] bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 b it-9 bit-8 note * 2 : the special register set is accessible only when lcr bit-7 is set to ?1?.
ST16C454/68c454 15 rev. 3.20 transmit (thr) and receive (rhr) holding reg- isters the serial transmitter section consists of an 8-bit transmit hold register (thr) and transmit shift register (tsr). the status of the thr is provided in the line status register (lsr). writing to the thr transfers the contents of the data bus (d7-d0) to the thr, providing that the thr or tsr is empty. the thr empty flag in the lsr register will be set to a logic 1 when the transmitter is empty or when data is transferred to the tsr. note that a write operation can be performed when the transmit holding register empty flag is set. the serial receive section also contains an 8-bit receive holding register, rhr. receive data is removed from the 454 by reading the rhr register. the receive section provides a mechanism to prevent false starts. on the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at 16x clock rate. after 7 1/2 clocks the start bit time should be shifted to the center of the start bit. at this time the start bit is sampled and if it is still a logic 0 it is validated. evaluating the start bit in this manner prevents the receiver from assembling a false charac- ter. receiver status codes will be posted in the lsr. interrupt enable register (ier) the interrupt enable register (ier) masks the inter- rupts from receiver ready, transmitter empty, line status and modem status registers. these interrupts would normally be seen on the int a-d output pins in the 16 mode, or on wire-or irq output pin, in the 68 mode. ier bit-0: this interrupt will be issued when the rhr is full, cleared when the rhr is empty. logic 0 = disable the receiver ready interrupt. (normal default condition) logic 1 = enable the receiver ready interrupt. ier bit-1: this interrupt will be issued whenever the thr is empty and is associated with bit-1 in the lsr register. logic 0 = disable the transmitter empty interrupt. (normal default condition) logic 1 = enable the transmitter empty interrupt. ier bit-2: this interrupt will be issued whenever a fully as- sembled receive character is transferred from the rsr to the rhr, data ready, lsr bit-0. logic 0 = disable the receiver line status interrupt. (normal default condition) logic 1 = enable the receiver line status interrupt. ier bit-3: logic 0 = disable the modem status register interrupt. (normal default condition) logic 1 = enable the modem status register interrupt. ier bit 4-7: not used - initialized to a logic 0. interrupt status register (isr) the 454 provides four levels of prioritized interrupts to minimize external software interaction. the interrupt status register (isr) provides the user with six inter- rupt status bits. performing a read cycle on the isr will provide the user with the highest pending interrupt level to be serviced. no other interrupts are acknowl- edged until the pending interrupt is serviced. when- ever the interrupt status register is read, the interrupt status is cleared. however it should be noted that only the current pending interrupt is cleared by the read. a lower level interrupt may be seen after rereading the interrupt status bits. the interrupt source table 7 (below) shows the data values (bit 0-5) for the four prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels:
ST16C454/68c454 16 rev. 3.20 table 7, interrupt source table priority [ isr bits ] source of the interrupt level bit-3 bit-2 bit-1 bit-0 1 0110lsr (r eceiver line status register) 2 0100 rxrdy (received data ready) 3 0010 txrdy ( transmitter holding register empty) 4 0000msr (m odem status register) isr bit-0: logic 0 = an interrupt is pending and the isr contents may be used as a pointer to the appropriate interrupt service routine. logic 1 = no interrupt pending. (normal default condi- tion) isr bit 1-3: (logic 0 or cleared is the default condition) these bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3 (see interrupt source table). isr bit 4-7: not used - initialized to a logic 0. line control register (lcr) the line control register is used to specify the asynchronous data communication format. the word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. lcr bit 0-1: (logic 0 or cleared is the default condi- tion) these two bits specify the word length to be transmit- ted or received. bit-1 bit-0 word l ength 00 5 01 6 10 7 11 8 lcr bit-2: (logic 0 or cleared is the default condition) the length of stop bit is specified by this bit in conjunction with the programmed word length. bit-2 word l ength stop bit length (bit time(s)) 0 5,6,7,8 1 1 5 1-1/2 1 6,7,8 2 lcr bit-3: parity or no parity can be selected via this bit. logic 0 = no parity. (normal default condition) logic 1 = a parity bit is generated during the transmis- sion, receiver checks the data and parity for transmis- sion errors. lcr bit-4: if the parity bit is enabled with lcr bit-3 set to a logic 1, lcr bit-4 selects the even or odd parity format. logic 0 = odd parity is generated by forcing an odd number of logic 1?s in the transmitted data. the receiver must be programmed to check the same format. (normal default condition) logic 1 = even parity is generated by forcing an even the number of logic 1?s in the transmitted. the receiver must be programmed to check the same format. lcr bit-5: if the parity bit is enabled, lcr bit-5 selects the forced parity format.
ST16C454/68c454 17 rev. 3.20 lcr bit-5 = logic 0, parity is not forced. (normal default condition) lcr bit-5 = logic 1 and lcr bit-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. lcr bit-5 = logic 1 and lcr bit-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. lcr lcr lcr parity selection bit-5 bit-4 bit-3 x x 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 force parity ?1? 1 1 1 forced parity ?0? lcr bit-6: when enabled the break control bit causes a break condition to be transmitted (the tx output is forced to a logic 0 state). this condition exists until disabled by setting lcr bit-6 to a logic 0. logic 0 = no tx break condition. (normal default condition) logic 1 = forces the transmitter output (tx) to a logic 0 for alerting the remote receiver to a line break condition. lcr bit-7: not used - initialized to a logic 0. modem control register (mcr) this register controls the interface with the modem or a peripheral device. mcr bit-0: logic 0 = force -dtr output to a logic 1. (normal default condition) logic 1 = force -dtr output to a logic 0. mcr bit-1: logic 0 = force -rts output to a logic 1. (normal default condition) logic 1 = force -rts output to a logic 0. mcr bit-2: this bit is used in the loop-back mode only. in the loop-back mode this bit is use to write the state of the modem -ri interface signal via -op1. mcr bit-3: ( used to control the modem -cd signal in the loop-back mode.) logic 0 = forces int (a-d) outputs to the three state mode during the 16 mode. (normal default condition) in the loop-back mode, sets -op2 (-cd) internally to a logic 1. logic 1 = forces the int (a-d) outputs to the active mode during the 16 mode. in the loop-back mode, sets -op2 (-cd) internally to a logic 0. mcr bit-4: logic 0 = disable loop-back mode. (normal default condition) logic 1 = enable local loop-back mode (diagnostics). mcr bit 5-7: not used - initialized to a logic 0. line status register (lsr) this register provides the status of data transfers between. the 454 and the cpu. lsr bit-0: logic 0 = no data in receive holding register. (normal default condition) logic 1 = data has been received and is saved in the receive holding register. lsr bit-1: logic 0 = no overrun error. (normal default condition) logic 1 = overrun error. a data overrun error occurred in the receive shift register. this happens when addi- tional data arrives while the rhr is full. in this case the previous data in the shift register is overwritten. note that under this condition the data byte in the receive shift register is not transferred into the rhr, therefore the data in the rhr is not corrupted by the error. lsr bit-2: logic 0 = no parity error. (normal default condition) logic 1 = parity error. the receive character does not have correct parity information and is suspect. in the rhr mode, this error is associated with the character
ST16C454/68c454 18 rev. 3.20 at the top of the rhr. lsr bit-3: logic 0 = no framing error. (normal default condition) logic 1 = framing error. the receive character did not have a valid stop bit(s). lsr bit-4: logic 0 = no break condition. (normal default condi- tion) logic 1 = the receiver received a break signal (rx was a logic 0 for one character frame time). lsr bit-5: this bit indicates that the 454 is ready to accept new characters for transmission. this bit causes the 454 to issue an interrupt to the cpu when the transmit holding register is empty and the interrupt enable is set. logic 0 = transmit holding register is not empty. (normal default condition) logic 1 = transmit holding register is empty. lsr bit-6: logic 0 = transmitter holding and shift registers are full. logic 1 = transmitter holding and shift registers are empty (normal default condition). lsr bit-7: not used - initialized to a logic 0. modem status register (msr) this register provides the current state of the control interface signals from the modem, or other peripheral device that the 454 is connected to. four bits of this register are used to indicate the changed information. these bits are set to a logic 1 whenever a control input from the modem changes state. these bits are set to a logic 0 whenever the cpu reads this register. msr bit-0: logic 0 = no -cts change (normal default condition) logic 1 = the -cts input to the 454 has changed state since the last time it was read. a modem status interrupt will be generated. msr bit-1: logic 0 = no -dsr change. (normal default condition) logic 1 = the -dsr input to the 454 has changed state since the last time it was read. a modem status interrupt will be generated. msr bit-2: logic 0 = no -ri change. (normal default condition) logic 1 = the -ri input to the 454 has changed from a logic 0 to a logic 1. a modem status interrupt will be generated. msr bit-3: logic 0 = no -cd change. (normal default condition) logic 1 = indicates that the -cd input to the has changed state since the last time it was read. a modem status interrupt will be generated. msr bit-4: -cts (active high, logical 1). normally msr bit-4 bit is the compliment of the -cts input. however in the loop-back mode, this bit is equivalent to the rts bit in the mcr register. msr bit-5: dsr (active high, logical 1). normally this bit is the compliment of the -dsr input. in the loop-back mode, this bit is equivalent to the dtr bit in the mcr register. msr bit-6: ri (active high, logical 1). normally this bit is the compliment of the -ri input. in the loop-back mode this bit is equivalent to the op1 bit in the mcr register. msr bit-7: cd (active high, logical 1). normally this bit is the compliment of the -cd input. in the loop-back mode this bit is equivalent to the op2 bit in the mcr register. scratchpad register (spr) the ST16C454 provides a temporary data register to store 8 bits of user information.
ST16C454/68c454 19 rev. 3.20 ST16C454 external reset conditions registers reset state ier ier bits 0-7=0 isr isr bit-0=1, isr bits 1-7=0 lcr lcr bits 0-7=0 mcr mcr bits 0-7=0 lsr lsr bits 0-4=0, lsr bits 5-6=1 lsr, bit 7=0 msr msr bits 0-3=0, msr bits 4-7= input signals signals reset state tx a-d high -rts a-d high -dtr a-d high int a-d three-state
ST16C454/68c454 20 rev. 3.20 symbol parameter limits limits units con ditions 3.3 5.0 min max min max ac electrical characteristics t a =0 - 70c (-40 - +85c for industrial grade packages), vcc=3.3 - 5.0 v 10% unless otherwise specified. t 1w, t 2w clock pulse duration 17 17 ns t 3w oscillator/clock frequency 8 24 mhz t 6s address setup time 5 0 ns t 7d -ior delay from chip select 10 10 ns t 7w -ior strobe width 35 25 ns t 7h chip select hold time from -ior 0 0 ns t 9d read cycle delay 40 30 ns t 12d delay from -ior to data 35 25 ns t 12h data disable time 25 35 15 ns t 13d -iow delay from chip select 10 10 ns t 13w -iow strobe width 35 25 ns t 13h chip select hold time from -iow 0 0 ns t 15d write cycle delay 40 30 ns t 16s data setup time 20 15 ns t 16h data hold time 5 5 ns t 17d delay from -iow to output 50 40 ns 100 pf load t 18d delay to set interrupt from modem 40 35 ns 100 pf load input t 19d delay to reset interrupt from -ior 40 35 ns 100 pf load t 20d delay from stop to set interrupt 1 1 rclk t 21d delay from -ior to reset interrupt 45 40 ns 100 pf load t 22d delay from stop to interrupt 45 40 ns t 23d delay from initial int reset to transmit 8 24 8 24 rclk start t 24d delay from -iow to reset interrupt 45 40 ns t 25d delay from stop to set -rxrdy 1 1 rclk t 26d delay from -ior to reset -rxrdy 45 40 ns t 27d delay from -iow to set -txrdy 45 40 ns t 28d delay from start to reset -txrdy 8 8 rclk t 30s address setup time 10 10 ns t 30w chip select strobe width 40 40 ns t 30h address hold time 15 15 ns t 30d read cycle delay 70 70 ns t 31d delay from -cs to data 15 15 ns t 31h data disable time 15 ns t 32s write strobe setup time 10 10 ns t 32h write strobe hold time 10 10 ns t 32d write cycle delay 70 70 ns
ST16C454/68c454 21 rev. 3.20 symbol parameter limits limits units con ditions 3.3 5.0 min max min max ac electrical characteristics t a =0 - 70c (-40 - +85c for industrial grade packages), vcc=3.3 - 5.0 v 10% unless otherwise specified. t 33s data setup time 20 15 ns t 33h data hold time 10 10 ns t r reset pulse width 40 40 ns n baud rate devisor 1 2 16 -1 1 2 16 -1 rclk
ST16C454/68c454 22 rev. 3.20 symbol parameter limits limits units con ditions 3.3 5.0 min max min max absolute maximum ratings supply range 7 volts voltage at any pin gnd - 0.3 v to vcc +0.3 v operating temperature -40 c to +85 c storage temperature -65 c to 150 c package dissipation 500 mw dc electrical characteristics t a =0 - 70c (-40 - +85c for industrial grade packages), vcc=3.3 - 5.0 v 10% unless otherwise specified. v ilck clock input low level -0.3 0.6 -0.5 0.6 v v ihck clock input high level 2.4 vcc 3.0 vcc v v il input low level -0.3 0.8 -0.5 0.8 v v ih input high level 2.0 2.2 vcc v v ol output low level on all outputs 0.4 v i ol = 5 ma v ol output low level on all outputs 0.4 v i ol = 4 ma v oh output high level 2.4 v i oh = -5 ma v oh output high level 2.0 v i oh = -1 ma i il input leakage 10 10 m a i cl clock leakage 10 10 m a i cc avg power supply current 3 6 ma c p input capacitance 5 5 pf r in internal pull-up resistance 3 15 k w note: see the symbol description table, for a listing of pins having internal pull-up resistors.
ST16C454/68c454 23 rev. 3.20 -cs r/-w d0-d7 t30s t30h t31h t31d t30d t30w 8654-rd-1 a0-a4 a0-a4 -cs r/-w d0-d7 t30s t30h t30w t32s t32h t32d t33s t33h 8654-wd-1 general write timing in 68 mode general read timing in 68 mode
ST16C454/68c454 24 rev. 3.20 a0-a2 -cs -ior d0-d7 t6s t7w t7d t7h t9d t12d t12h x552-rd-1 active data valid address active a0-a2 -cs -iow d0-d7 t6s t13w t13d t13h t15d t16s t16h x552-wd-1 valid address active active data general write timing in 16 mode general read timing in 16 mode
ST16C454/68c454 25 rev. 3.20 t3w t1w t2w external clock x654-ck-1 -iow -rts -dtr -cd -cts -dsr int -ior -ri t17d t18d t18d t19d t18d x552-md-1 active active change of state change of state active active active change of state change of state change of state active active external clock timing modem input/output timing
ST16C454/68c454 26 rev. 3.20 stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 5 data bits 6 data bits 7 data bits start bit rx next data start bit int -ior t20d t21d 16 baud rate clock x552-rx-1 active active receive timing
ST16C454/68c454 27 rev. 3.20 stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 5 data bits 6 data bits 7 data bits start bit tx next data start bit int t22d t24d 16 baud rate clock x552-tx-1 -iow t23d active active tx ready active transmit timing
ST16C454/68c454 28 rev. 3.20
package dimensions
notice exar corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circum- stances. copyright 1994 exar corporation reproduction, in part or whole, without the prior written consent of exar corporation is prohibited.

▲Up To Search▲

Price & Availability of ST16C454

	To Download ST16C454 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .